(a) Field of the Invention
The present invention relates to a device and method for driving a plasma display panel (PDP).
(b) Description of the Related Art
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. Depending on its size, a PDP can include anywhere from several scores to millions of pixels arranged in a matrix pattern. A PDP is classified as a direct current (DC) type or an alternating current (AC) type based on its discharge cell structure and the waveform of the driving voltage applied thereto.
The waveform for driving an AC type PDP includes a reset period, an addressing period, a sustain period, and an erase period, in temporal sequence.
The reset period is for initiating the status of each cell so as to facilitate the addressing operation. The addressing period is for selecting turn-on/off cells and applying an address voltage to the turn-on cells (i.e., addressed cells) to accumulate wall charges. The sustain period is for applying sustain pulses and causing a discharge for displaying an image on the addressed cells. The erase period is for reducing the wall charges of the cells to terminate the sustain.
In the AC type PDP, the scan and sustain electrodes for sustaining act as a capacitance load, so capacitance exists between the scan and sustain electrodes. Such capacitance may be referred to as panel capacitance and equivalently represented by a panel capacitor. A driver circuit for applying sustain pulses to the panel capacitor, for example, is suggested by Kishi et al. (Japanese Patent No. 3201603).
The driver circuit suggested by Kishi et al. alternately applies voltages Vs/2 and −Vs/2 to the Y electrode of the panel capacitor by using a capacitor and a voltage source for supplying a voltage Vs/2 that is one half of the voltage Vs necessary for sustaining. More specifically, the driver circuit applies a voltage of Vs/2 to the Y electrode of the panel capacitor through the voltage source, and charges a voltage Vs/2 in the capacitor. Then, the capacitor is coupled between the ground terminal and the Y electrode of the panel capacitor to apply a voltage −Vs/2 to the Y electrode of the panel capacitor.
In this manner, the positive voltage +Vs/2 and the negative voltage −Vs/2 can be alternately applied to the Y electrode. Likewise, the positive voltage +Vs/2 and the negative voltage −Vs/2 can be alternately applied to the X electrode. The respective voltages ±Vs/2 applied to the X and Y electrodes are phase-inverted to each other, so the voltage Vs/2 necessary for sustaining is applied to both terminals of the panel capacitor.
This driver circuit can be used only for the PDP using the pulse swinging between −Vs/2 and Vs/2, and the withstand voltage of transistors cannot be sustained at Vs/2 because of the characteristics of the transistors. Moreover, this driver circuit requires a capacitor having high capacity to store a voltage used for the negative voltage and causes a considerable amount of in-rush current during starting due to the capacitor.